1. Field of the Invention
The present invention relates to a PLL (phase-lock loop) circuit that generates a signal that is in phase with a signal supplied from the outside of the circuit.
2. Prior Art
The superimposing technique is known which is used to superimpose an image representing channels or clock, for example, which is produced by an image display device, on an image or picture of television or VCR, to display superimposed images. While display control of a television picture, or the like, is performed in synchronization with a horizontal synchronizing signal included in a picture signal, display control of channel or other representation superimposed on the television picture by the superimposing technique needs to be also performed in synchronization with the horizontal synchronization signal, so that the channel or other representation does not fluctuate or oscillate relative to the television picture. To meet with this need, a PLL circuit is generally used to produce a dot clock that is in phase with the horizontal synchronizing signal, and the image display device outputs an image signal for channel or other representation in synchronization with the dot clock.
As known in the art, the PLL circuit is a loop circuit that consists essentially of a phase comparator, a low pass filter (which will be referred to as LPF), and a voltage-controlled oscillator (which will be referred to as VCO). To provide a dot clock that is in phase with the horizontal synchronizing signal of the picture signal, the horizontal synchronizing signal is supplied to one of input terminals of the phase comparator of the PLL circuit. On the other hand, an output signal of VCO is divided by a frequency divider, and an output signal of this frequency divider is supplied to the other input terminal of the phase comparator. The phase comparator outputs a phase error signal that represents a phase error between the output signal of the frequency divider and the horizontal synchronizing signal. This phase error signal is supplied to VCO via LPF, and the oscillation frequency of the output signal of VCO is controlled so that the phase error or difference between the output signal of the frequency divider and the synchronizing signal is reduced. As this control proceeds under a condition where the synchronizing signal is stably supplied with a constant frequency, the phase error between the output signal of the frequency divider and the synchronizing signal is reduced with time, and the oscillation frequency of VCO is locked or fixed at a point of time when the phase error becomes zero. In this locked state, the output signal of VCO is in phase with the horizontal synchronizing signal, and therefore this output signal is used as a dot clock.
In the meantime, the latest model of television systems installed on automobiles, which have been rapidly prevailing in these days, is now equipped with a system, called car multivision, for displaying in-car information (such as control information about an audio system or air conditioning).
This system employs the superimposing technique as described above to superimpose the in-car information produced by an image display device onto a television image to thereby display superimposed images. In this case, the system may not be able to receive the horizontal synchronization signal of the picture signal at a constant frequency, depending upon the receiving condition of radio waves, and the frequency of the horizontal synchronizing signal may temporarily fluctuate to a great extent.
If such a fluctuation in the frequency of the horizontal synchronizing signal occurs while the PLL circuit is held in the locked state, the oscillation frequency of VCO changes significantly due to a change in the phase error signal generated from the phase comparator, and the operation of the PLL circuit comes out of the locked state.
With the operation of the PLL circuit thus being out of the locked state, even if the horizontal synchronizing signal resumes its normal frequency, it still takes some time for the dot clock produced by the PLL circuit to be in phase with the horizontal synchronizing signal having the normal frequency. As a result, there arises a period in which the dot clock produced by the PLL circuit is out of phase with the horizontal synchronizing signal, and disturbance may occur in the image representing in-car information that is superimposed on the television picture for display.
While the illustrated example is concerned with the superimposing technique, the above problem is not limited to the case where the PLL circuit is used for controlling superimposing operations, but generally encountered in controls using the PLL circuit where a fluctuation occurs in the frequency of a reference signal (external synchronizing signal) that provides a basis for phase synchronization.